a) Field of the Invention
The present invention relates to a semiconductor non-volatile memory such as a flash memory, EPROM, or EEPROM. More particularly, the present invention relates to a technology suitably applied to method and apparatus for determining a deterioration of stored data in the semiconductor non-volatile memory and refreshing the data deteriorated non-volatile memory so as to protect memory content of the non-volatile memory and the memory itself.
b) Description of the Related Art
A Japanese Patent Application First Publication (non-examined) No. Heisei 3-238697 published on Oct. 24, 1991 exemplifies a previously proposed single-chip microcomputer having a non-volatile memory such as EEPROM (Electrically Erasable Programmable Read Only Memory).
A semiconductor device disclosed in the above-identified Japanese Patent Application First Publication is constituted by a CPU (Central Processing Unit), a memory matrix, a timer, and a write circuit including a control circuitry. The CPU is connected to the memory matrix, the timer, and the write circuit which is connected to the memory matrix and the timer. The memory matrix is constituted by a plurality of memory cells of transistors and is constituted by a flash memory or Programmable ROM such as the EEPROM or EPROM (Erasable Programmable Read Only Memory). Each non-volatile memory transistor is constituted by a bit.
Each memory cell, i.e., each non-volatile memory transistor used in Programmable ROM is generally provided with a floating gate surrounded by an insulating film. In the PROM, a high threshold value voltage condition developed due to an injection of electrons toward the floating gate is a data write and a low threshold value voltage condition developed due to a draw out of the electrons from the floating gate is a data erasure.
Each memory cell, i.e., each non-volatile memory transistor used in Programmable ROM is generally provided with a floating gate surrounded by an insulating film.
In the programmable ROM, a high threshold value voltage condition developed due to an injection of electrons to the floating gate is a data write and a low threshold value voltage condition developed due to a draw out of the electrons from the floating gate is a data erasure.
However, in such a PROM as described above, the following three problems are raised. Consequently, it cannot be guaranteed that stored data in the PROM are continued to be stably retained. That is to say, at first, in a case where an environmental temperature of the PROM in use is considerably high, e.g., in a case where the PROM is used for an automotive vehicle purpose (is used in an engine compartment of the automotive vehicle), it becomes easy for charges within the floating gate to be vanished. This is called a worsening of a retention characteristic of the PROM.
Secondly, a disturb occurs which is caused by a voltage application to a corresponding bit line or a corresponding word line when the data is written into another bit or the written data is erased.
Thirdly, a soft write occurs which is caused by electrons injections into the floating gate when the data in the corresponding bit is read.
To cope with the above-described three problems, in the semiconductor device disclosed in the above-identified Japanese Patent Application First Publication, a refresh (rewrite) operation is carried out to prevent the stored data from being inverted (or reversed). This refresh operation will be explained below briefly.
The CPU supplies a data rewrite signal to the timer and the write circuit in accordance with a program stored in the memory matrix. At this time, the timer supplies a time duration required to rewrite the data in the respective bits of the memory matrix sequentially to the write circuit and, then, the write circuit sequentially rewrites (refreshes) the data in the respective bits. The refresh operation is carried out before the data in the respective bits in the memory matrix are vanished so that the data reversal can be prevented.